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Tattvam AI secures $1.7 Mn in pre-seed round led by Seedcamp

Entrackr · 8h ago

Medial

Tattvam AI, a deeptech startup building AI systems to automate semiconductor chip design, has raised $1.7 million in a pre-seed funding round led by Seedcamp, with participation from EWOR, Entropy Industrial Ventures, Concept Ventures, and semiconductor angel Stan Boland. The fresh capital will be used to ramp up the engineering team, accelerate research, bring the company’s first product to market, and expand partnerships with leading chip design teams, Tattvam AI said in a press release. Co-founded last year by Bragadeesh Suresh Babu and Lannan Jiang, Tattvam AI aims to transform semiconductor development by enabling chips to be designed faster and customized for specific applications, improving performance at the system level. The startup is introducing a novel approach to chip design by building an AI system that deeply understands circuit structures and autonomously solves complex design tasks, significantly reducing development cycles. Unlike general-purpose chips designed to handle a wide range of tasks, custom silicon refers to processors optimized for specific workloads such as AI training or inference. These purpose-built chips can deliver up to 100x performance improvements over general-purpose hardware like GPUs for targeted applications, while often consuming less power. According to the company, Tattvam AI is developing a reasoning model that understands circuits from first principles, including constraints, trade-offs, and interdependencies, similar to how a world-class engineer operates but in a fraction of the time. By automating and accelerating the use of EDA tools, the startup aims to cut chip design timelines from years to weeks. Tattvam AI plans to launch its first product in the coming months as it works with partners to accelerate the development of next-generation chips. By automating key parts of the design process, the company aims to make custom silicon more accessible, reduce development costs, and enable rapid iteration on chip designs.